1. Field of the Invention
The present invention relates to a transistor-type protection device that can be turned on and remove noise when noise at a predetermined or higher level is superimposed on wiring of a connected circuit. Further, the present invention relates to a semiconductor integrated circuit in which the transistor-type protection device and a circuit to be protected are integrated on the same substrate.
2. Description of Relate Art
Generally, a semiconductor integrated circuit includes a protection circuit for electrostatic discharge (ESD) for protecting an internal circuit from static electricity entering from an external terminal.
The protection circuit connects an ESD protection device between wires where static electricity tends to be superimposed like that between the power supply line and the GND line of the internal circuit.
As the ESD protection device, typically, a GGMOS (Gate-Grounded MOSFET) using a MOSFET forming the internal circuit or thyristor is used.
An example of the protection device using a GGMOS is disclosed in JP-A-2002-9281. Further, an example of the protection device using a thyristor is disclosed in M. P. J. Mergens et al., “Diode-Triggered SCR (DTSCR) for RF-ESD Protection of BICMOS SiGe HBTs and CMOS Ultra-Thin Gate Oxides”, in IEDM' 03 Tech. Digest, pp. 21.3.1-21.3.4, 2003.
An advantage of using a thyristor as the protection device is that the on-resistance is low. Accordingly, the thyristor is suitable for protection of small low-withstand-voltage micro MOSFET. Further, the thyristor is suitable for flowing large current because it can secure a large sectional area of current path.
However, the thyristor has a disadvantage of having a high trigger voltage. If the trigger voltage is high, the internal circuit is broken before the thyristor is turned on.
On this account, various proposals have been made for reducing the trigger voltage.
For example, M. P. J. Mergens et al. discloses an example of a technology using forward current of PN junction. If the technology is applied, the trigger voltage and the hold voltage can be controlled by the number of diodes and the design of the protection device is easy.
However, in the technology disclosed in M. P. J. Mergens et al., the diodes are constantly biased forward, and the statistic leak current is large. The leak current is sensitive to the device temperature and rapidly increases with rise of the device temperature.
Further, in the technology disclosed in M. P. J. Mergens et al., if the number of diodes is reduced for obtainment of the low trigger voltage, the leak current is increased. Accordingly, it may be impossible to use the technology for the application with severe restrictions on power consumption.
On the other hand, the protection circuit using a GGMOS is formed with elongated wiring within the integrated circuit (IC) between the power supply voltage line and the GND line where electrostatistic noise tends to be superimposed as shown in FIG. 1 of JP-A-2002-9281. Here, each of a PMOS transistor and an NMOS transistor of the same type as the inverter of the internal circuit has a GGMOS configuration and series-connected between the VDD line and the GND line.
In FIGS. 3 and 14 of JP-A-2002-9281, sectional structure diagrams of a GGMOSFET are shown.
According to the description of JP-A-2002-9281, there is a low-density semiconductor region led out to the outside of a side wall spacer from a gate electrode in a gate length direction. In JP-A-2002-9281, signs “(7b, 8b)” indicate the low-density semiconductor region. The low-density semiconductor region is formed to be a non-silicide region.
According to the description of JP-A-2002-9281, if the low-density semiconductor region is non-silicided, the higher diffusion resistance than that in the case where a high-density semiconductor region is non-silicided is obtained. When a carrier path is secured by the high diffusion resistance, a current path S1 is produced from the LDD end (low-density semiconductor region end) to the source side. Then, the current beyond the flow in the current path S1 is allowed to flow in a new current path S2 starting from a drain region at high impurity density to the source side. Thereby, current is distributed and the resistance to electrostatic breakdown of the GGMOS is improved.